1. Field of the Invention
This invention relates to a semiconductor device formed with an MOS semiconductor component or an MNOS or MONOS semiconductor non-volatile memory cell or the like formed on a semiconductor substrate including a supporting substrate, an insulating film (BOX: Buried Oxide) on the supporting substrate and a semiconductor layer on the insulating film, and to a method of fabricating the semiconductor device.
2. Description of the Related Art
Among known types of semiconductor devices are those that use a silicon-on-insulator (SOI) substrate, i.e., a substrate formed of a supporting substrate, an insulating film on the supporting substrate and a semiconductor layer on the insulating film.
Since the semiconductor device using an SOI substrate can achieve total insulation and isolation between the component parts, it can suppress latch-up (malfunction between adjacent transistors) and radiation-induced soft errors.
Moreover, if the semiconductor layer formed on the insulating film in such a semiconductor device is reduced to a thin film, the depletion layer charge comes to be governed mainly by the gate potential. This provides such effects as suppression of the short-channel effect and improvement in the current drive performance.
An example of a prior-art semiconductor device using an SOI substrate will be explained with reference to the sectional view of FIG. 38.
The SOI substrate consists of a supporting substrate 1, an insulating film 2 and a semiconductor layer 3. The periphery and undersurface of the semiconductor layer 3 are completely insulated and isolated by a field oxide film 31 and the insulating film 2.
An MOS semiconductor component is constituted by forming a gate oxide film 14 on a channel region 7 of the semiconductor layer 3, a gate (electrode) 8 on the gate oxide film 14, and a source 6 and a drain 5 consisting of high-concentration impurity layers at the regions (source region and drain region) on opposite sides of the gate 8. The source 6 and the drain 5 are both in contact with the insulating film 2.
Reference numeral 32 designates an interlevel insulator film formed with contact holes 33 at which interconnecting electrodes 34, 35 are provided in connection with the source 6 and the drain 5. An interconnecting electrode is also provided in connection with the gate 8 at a different sectional position from that shown in FIG. 38.
The problematic parasitic capacitance that arises in a semiconductor device using a bulk silicon substrate and no insulating film 2, namely, the parasitic capacitance of the PN junction formed between the bulk silicon substrate and the high-concentration impurity layers of the source and drain, also arises in this semiconductor device using the SOI substrate consisting of the supporting substrate 1, the insulating film 2 and the semiconductor layer 3.
As shown in the configuration of FIG. 38, therefore, the semiconductor layer 3 is formed as a thin film of a thickness of 100 nm or less and the high-concentration impurity layers of the source 6 and the drain 5 are formed to contact the insulating film 2, in order to limit the PN junction formed between the high-concentration impurity layers and the semiconductor layer 3 to the channel region 7 immediately under the gate 8 of the semiconductor layer 3.
The MOS semiconductor component of the semiconductor device shown in FIG. 38 thus has a thin semiconductor layer 3 that is no more than 100 nm thick. The impurity of the high-concentration impurity layers of the source 6 and the drain 5 consequently reach as far as the insulating film 2.
Since the channel region 7 of the semiconductor layer 3 is therefore completely surrounded by the source 6, the drain 5 and the field oxide film 31, the semiconductor layer 3 of the channel region 7 floats electrically.
When an MOS semiconductor component, e.g., an N-channel MOS semiconductor component, having this electrically floating configuration is driven, the holes created in the depletion layer near the drain 5 accumulate in the semiconductor layer 3 to raise the overall potential, amplify injection of electrons from the source 6 and alter the current characteristic.
The change in the current characteristic becomes more pronounced with increasing source voltage since the electric field near the drain region increases with increasing source voltage.
Circuit regions constituted of this semiconductor component which are subject to high drive voltages, e.g. input/output protection circuits, step-down circuits, step-up circuits and the like, are therefore degraded in reliability.
Since the high-concentration impurity layers of the source 6 and the drain 5 extend to the interface with the insulating film 2, moreover, leak current occurs owing to the interface state density present at the interface between the semiconductor layer 3 and the insulating film 2. This leak current becomes pronounced under exposure to radiation.
A semiconductor device formed with a semiconductor non-volatile memory cell and having a configuration like the MOS semiconductor component just explained will now be explained with reference to the sectional view of FIG. 39.
Portions in FIG. 39 corresponding to those in FIG. 38 are assigned the same reference symbols as those in FIG. 38 and are not explained again here.
In this semiconductor device, a memory gate insulating film consisting of a tunnel oxide film 11, a silicon nitride film 12 and a top oxide film 13 is formed on the channel region 7 of the semiconductor layer 3 and the gate 8 is formed on the memory gate insulating film, thereby configuring an MONOS semiconductor non-volatile memory cell. The high-concentration impurity layers of the source 6 and the drain 5 formed by self-alignment on opposite sides of the gate 8 contact the insulating film 2. In other respects the configuration is the same as that of the semiconductor device shown in FIG. 38.
In the semiconductor layer shown in FIG. 39, parasitic capacitance is also suppressed by forming the semiconductor layer 3 as a thin film of a thickness of 100 nm or less and forming the high-concentration impurity layers of the source 6 and the drain 5 to contact the insulating film 2, thereby limiting the PN junction formed between the high-concentration impurity layers and the semiconductor layer 3 to the channel region 7 immediately under the gate 8 of the semiconductor layer 3.
This MONOS non-volatile memory cell becomes an MNOS non-volatile memory cell if the memory gate insulating film is formed of only the tunnel oxide film 11 and the silicon nitride film 12 and the top oxide film 13 is omitted.
In this MONOS or MNOS non-volatile memory cell, as in the MOS semiconductor component shown in FIG. 38, the semiconductor layer 3 of the channel region 7 floats electrically.
When data are written to or erased from the MONOS or MNOS non-volatile memory cell, therefore, the electric potential at the channel region 7 is unstable. This may cause operational errors.
This invention was accomplished to overcome the problems explained in the foregoing. The specific object of the invention is to provide a semiconductor device and a method of fabricating the same which enable the circuit regions of an MOS semiconductor component where the source voltage is high to operate with improved reliability and ensure that the writing and erasure of data to or from an MONOS or MNOS non-volatile memory cell are effected reliably.